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TC55VL836FF-83 2003-02-20 1/21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 99 97 95 93 91 89 87 85 83 81 100 98 96 94 92 90 88 86 84 82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 34 36 38 40 42 44 46 48 50 31 33 35 37 39 41 43 45 47 49 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /we /cke /oe adv nc a17 a8 a9 i/op2 i/o16 i/o15 v ddq v ssq i/o14 i/o13 i/o12 i/o11 v ssq v ddq i/o10 i/o9 v ss v ss v dd zz i/o8 i/o7 v ddq v ssq i/o6 i/o5 i/o4 i/o3 v ssq v ddq i/o2 i/o1 i/op1 i/op3 i/o17 i/o18 v ddq v ssq i/o19 i/o20 i/o21 i/o22 v ssq v ddq i/o23 i/o24 v ss v dd v dd v ss i/o25 i/o26 v ddq v ssq i/o27 i/o28 i/o29 i/o30 v ssq v ddq i/o31 i/o32 i/op4 mode a5 a4 a3 a2 a1 a0 nu nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 a16 toshiba mos digital integrated circuit silicon gate cmos 262,144-word by 36-bit synchronous no-turnaround static ram description the tc55vl836ff is a synchronous static random access memory (sram) organized as 262,144 words by 36 bits. ntram tm (no-turnaround sram) offers high bandwidth by eliminating dead cycles during the transition from a read to a write and vice versa. all inputs except output enable oe and the snooze pin zz are synchronized with the rising edge of the clk input. a read operation is initiated by the adv address advanced input signal ; the input from the address pins and all control pins except the oe and zz pins are loaded into the internal registers on the rising edge of clk in the cycle in which adv is asserted. the output data is available in the same clock cycle as that in which adv is asserted. write operations are internally self-timed and are initiated by the rising edge of clk in the cycle in which adv is asserted. the input from the address pins and all control pins except the oe and zz pins are loaded into the internal registers on the rising edge of clk in the cycle in which adv is asserted. input data is loaded in the cycle following the cycle in which adv is asserted. byte write enables ( bw1 to bw4 ) allow from one to four byte write operations to be performed. a 2-bit burst address counter and control logic are integrated into this sram. the tc55vl836ff uses a single power supply (3.3 v) or dual power supplies (3.3 v for core and 2.5 v for output buffer) and is available in a 100-pin low-profile plastic qfp (lqfp). features ? organized as 262,144 words by 36 bits ? fast cycle time of 12 ns minimum (83 mhz maximum) ? fast access time of 9 ns maximum (from clock edge to data output) ? no-turnaround operation with flow-through data output ? 2-bit burst address counter (support for interleaved or linear burst sequences) ? synchronous self-timed write ? byte write control ? snooze mode pin (zz) for power down ? lvttl-compatible interface ? single power supply (3.3 v) or dual power supplies (3.3 v for core and 2.5 v for output buffer) ? available in 100-pin lqfp package (lqfp100-p-1420-0.65k ; pitch:0.65 mm, height:1.6 mm, weight:0.56 grams (typical)) pin assignment (top view) pin names clk clock input a0 to a17 address inputs ce , ce2 , ce2 chip enable inputs oe output enable input we write enable input bw1 to bw4 byte write enable adv address advance input cke clock enable zz snooze input i/o1 to i/o32 data inputs/outputs i/op1 to i/op4 parity data inputs/outputs mode mode select input nc no connection nu not usable v dd power supply for core v ddq power supply for output buffer v ss ground for core v ssq ground for output buffer note : ntram tm and no-turnaround random access memory are trademarks of samsung electronics co., ltd..
TC55VL836FF-83 2003-02-20 2/21 block diagram binary counter and logic a0 /a1 read/write control logic & coherency control logic memory cell array 256 k 36 bits (9,437,184 bits) address register address register 1 din register 18 18 36 36 36 ad v bw1 to bw4 we data-out control a0 to a17 mode data-out control 36 i/o, i/op cl k cke ce2 ce oe ce2
TC55VL836FF-83 2003-02-20 3/21 pin descriptions pin number symbol type description 89 clk input (na) clock input all synchronous input signals are registered on the rising edge of clk. when the chip is enabled, address inputs and control pins except for oe and zz must meet the specified setup and hold times with respect to the clk rising edge. 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83 a0 to a17 input (synchronous) address inputs these address inputs are registered on the rising edge of clk. when the chip is enabled, address inputs must meet the specified setup and hold times with respect to the clk rising edge. 98 ce input (synchronous) chip enable input this active-low signal controls the chip status (enabled or disabled). it is sampled only when a new external address is loaded. 92 ce2 input (synchronous) chip enable input this active-low signal controls the chip status (enabled or disabled). it is sampled only when a new external address is loaded. 97 ce2 input (synchronous) chip enable input this active-high signal controls the chip status (enabled or disabled). it is sampled only when a new external address is loaded. 86 oe input (asynchronous) output enable input this active-low signal controls all 36 bits of the i/o output buffer. 88 we input (synchronous) write enable input this active-low input controls read/write operations. 93, 94, 95, 96 bw1 to bw4 input (synchronous) byte write enable these active-low inputs control byte write operations when a write cycle is active. a byte write pin controls i/o pins as follows. bw1 : i/o1 to i/o8, i/op1 bw2 : i/o9 to i/o16, i/op2 bw3 : i/o17 to i/o24, i/op3 bw4 : i/o25 to i/o32, i/op4 85 adv input (synchronous) address advance input this is used to load the internal registers with the input from the address and control signals when it is low on the rising edge of clk. when it is high, the internal burst address counter is incremented. the external address inputs are ignored when this signal is high. 87 cke input (synchronous) clock enable when high, clk input is ignored and outputs retain the same state. 64 zz input (asynchronous) snooze input this active-high signal is used to place the device into sleep mode (low-power standby mode). when low, the device remains in the active state. when high, the device goes into the sleep state and memory data is retained. after this signal has been de-asserted, the device will wake up when a read or write operation is initiated by adv.
TC55VL836FF-83 2003-02-20 4/21 pin number symbol type description 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 i/o1 to i/o32 i/o (synchronous) data input/output 51, 80, 1, 30 i/op1 to i/op4 i/o (synchronous) parity data input/output 31 mode input (synchronous) mode select input this signal selects the burst sequence. when high, the burst sequence is interleaved. when low, it is linear. 39, 42, 43, 84 nc nc not connected 38 nu input (asynchronous) not usable 15, 16, 41, 65, 91 vdd supply power supply for core 4, 11, 20, 27, 54, 61, 70, 77 vddq supply power supply for output buffers 14, 17, 40, 66, 67, 90 vss ground ground for core 5, 10, 21, 26, 55, 60, 71, 76 vssq ground ground for output buffers
TC55VL836FF-83 2003-02-20 5/21 operating mode (1) synchronous input truth table operation we adv ce bw addr. used cke zz i/o (5) read (begin burst) h l select x external l l output read (continue burst) x h x x internal l l output write (begin burst) l l select l external l l input write (continue burst) x h x l internal l l input nop/write abort (begin burst) l l select h x l l hi-z write abort (continue burst) x h x h internal l l hi-z deselected x l deselect x x l l hi-z deselect continue (note 2) x h x x x l l hi-z ignore clock edge (note 3) x x x x x h l previous value snooze x x x x x x h hi-z notes: 1. h means logical high and l means logical low. x means don?t care. 2. a deselect continue cycle can only be entered if a deselect cycle is executed before it. 3. when the ignore clock edge command is asserted during a read operation, the output data for the previous cycle still appear on the i/o pins. when the command is asserted during a write operation, the i/o pins remain at hi-z and the write operation is not executed. 4. all synchronous inputs must exhibit adequate setup and hold times either side of the rising edge of the clk pin. 5. the data output appears in the same cycle as that in which the read command is asserted. data input is triggered on the rising edge of clk in the next following the one in which the write command is asserted. 6. zz input is asynchronous, but is included is this table. (2) write enable truth table operation we bw1 bw2 bw3 bw4 i/o1 to i/o8 i/op1 i/o9 to i/o16 i/op2 i/o17 to i/o24 i/op3 i/o25 to i/o32 i/op4 read h x x x x output output output output l l l l l input input input input l l h h h input hi-z hi-z hi-z l h l h h hi-z input hi-z hi-z l h h l h hi-z hi-z input hi-z l h h h l hi-z hi-z hi-z input write l h h h h hi-z hi-z hi-z hi-z notes: 1. h means logical high and l means logical low. x means don?t care. (3) asynchronous inputs truth table operation oe zz i/o l l dout read h l hi-z write x l din, hi-z h l hi-z stop clock (note 2) l l low-z snooze (note 3) x h hi-z notes: 1. h means logical high and l means logical low. x means don?t care. 2. the stop clk mode achieves low-power standby by stopping the input clock. 3. the snooze mode achieves low-power standby by asserting the zz pin. 4. the cycle immediately prior to a snooze brought about by the zz pin must be a read mode or deselect mode cycle. 5. memory data is retained during snooze mode cycles.
TC55VL836FF-83 2003-02-20 6/21 (4) burst sequence mode pin burst operation l linear burst order h or nc interleaved burst order a) linear burst sequence (mode input = v ss ) bit order : a 17 - - - - - - - - - - - a 1 a 0 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) xx - - - - - - xx00 xx - - - - - - xx01 xx - - - - - - xx10 xx - - - - - - xx11 xx - - - - - - xx01 xx - - - - - - xx10 xx - - - - - - xx11 xx - - - - - - xx00 xx - - - - - - xx10 xx - - - - - - xx11 xx - - - - - - xx00 xx - - - - - - xx01 xx - - - - - - xx11 xx - - - - - - xx00 xx - - - - - - xx01 xx - - - - - - xx10 b) interleaved burst sequence (mode input = v dd or nc) bit order : a 17 - - - - - - - - - - - a 1 a 0 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) xx - - - - - - xx00 xx - - - - - - xx01 xx - - - - - - xx10 xx - - - - - - xx11 xx - - - - - - xx01 xx - - - - - - xx00 xx - - - - - - xx11 xx - - - - - - xx10 xx - - - - - - xx10 xx - - - - - - xx11 xx - - - - - - xx00 xx - - - - - - xx01 xx - - - - - - xx11 xx - - - - - - xx10 xx - - - - - - xx01 xx - - - - - - xx00 device operation (1) read operation cycle address we bw adv ce oe cke i/o operation n a0 h x l l x l x address & control valid n + 1 x x x x x l l q0 read out a0 notes: 1. h means logical high and l means logical low. x means don?t care. q is data output. (2) burst read operation cycle address we bw adv ce oe cke i/o operation n a0 h x l l x l x address & control valid n + 1 x x x h x l l q0 read out a0 n + 2 x x x h x l l q0 + 1 read out a0 + 1 n + 3 x x x h x l l q0 + 2 read out a0 + 2 n + 4 x x x h x l l q0 + 3 read out a0 + 3 n + 5 a1 h x l l l l q0 read out a0 n + 6 x x x h x l l q1 read out a1 n + 7 a2 h x l l l l q1 + 1 read out a1 + 1 notes: 1. h means logical high and l means logical low. x means don?t care. q is data output.
TC55VL836FF-83 2003-02-20 7/21 (3) write operation cycle address we bw adv ce oe cke i/o operation n a0 l l l l x l x address & control valid n + 1 x x x x x x l d0 write to a0 notes: 1. h means logical high and l means logical low. x means don?t care. d is data input. (4) burst write operation cycle address we bw adv ce oe cke i/o operation n a0 l l l l x l x address & control valid n + 1 x x l h x x l d0 write a0 n + 2 x x l h x x l d0 + 1 write a0 + 1 n + 3 x x l h x x l d0 + 2 write a0 + 2 n + 4 x x l h x x l d0 + 3 write a0 + 3 n + 5 a1 l l l l x l d0 write a0 n + 6 x x l h x x l d1 write a1 n + 7 a2 l l l l x l d1 + 1 write a1 + 1 notes: 1. h means logical high and l means logical low. x means don?t care. d is data input. (5) read operation with clock enable cycle address we bw adv ce oe cke i/o operation n a0 h x l l x l x address & control valid n + 1 x x x x x x h x ignore cycle n + 2 a1 h x l l l l q0 a0 read out n + 3 x x x x x l h q0 ignore clock n + 4 x x x x x l h q0 ignore clock n + 5 a2 h x l l l l q1 read out a1 n + 6 a3 h x l l l l q2 read out a2 n + 7 a4 h x l l l l q3 read out a3 notes: 1. h means logical high and l means logical low. x means don?t care. q is data output.
TC55VL836FF-83 2003-02-20 8/21 (6) write operation with clock enable cycle address we bw adv ce oe cke i/o operation n a0 l l l l x l x address & control valid n + 1 x x x x x x h x ignore clock n + 2 a1 l l l l x l d0 write a0 n + 3 x x x x x x h x ignore clock n + 4 x x x x x x h x ignore clock n + 5 a2 l l l l x l d1 write a1 n + 6 a3 l l l l x l d2 write a2 n + 7 x x x x x x l d3 write a3 notes: 1. h means logical high and l means logical low. x means don?t care. d is data input. (7) read operation with chip enable cycle address we bw adv ce oe cke i/o operation n a0 h x l l x l x address & control valid n + 1 x x x l h l l q0 read a0 n + 2 a1 h x l l x l z deselect n + 3 x x x l h l l q1 read a1 n + 4 x x x l h x l z deselect n + 5 a2 h x l l x l z deselect n + 6 x x x l h l l q2 read a2 n + 7 x x x l h x l z deselect notes: 1. h means logical high and l means logical low. x means don?t care. q is data output. z means hi-z. (8) write operation with chip enable cycle address we bw adv ce oe cke i/o operation n a0 l l l l x l x address & control valid n + 1 x x x l h x l d0 write a0 n + 2 a1 l l l l x l z deselect n + 3 x x x l h x l d1 write a1 n + 4 x x x l h x l z deselect n + 5 a2 l l l l x l z deselect n + 6 x x x l h x l d2 write a2 n + 7 x x x l h x l z deselect notes: 1. h means logical high and l means logical low. x means don?t care. d is data input. z means hi-z.
TC55VL836FF-83 2003-02-20 9/21 maximum ratings symbol rating value unit v dd power supply voltage ? 0.5 to 4.6 v v ddq output buffer power supply voltage ? 0.5 to v dd + 0.5 ( 4.6 v max) v v in input terminal voltage ? 0.5 * to 4.6 v v i/o input/output terminal voltage ? 0.5 * to v ddq + 0.5 ** ( 4.6 v max) v p d power dissipation 1.5 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 65 to 150 c t opr operating temperature ? 10 to 85 c * : ? 1.0 v with a pulse width of 20% of t kc min (3 ns max) ** : v ddq + 1.0 v with a pulse width of 20% of t kc min (3 ns max) dc recommended operating conditions (ta = = = = 0 to 70c) symbol parameter min typ. max unit v dd power supply voltage 3.135 3.3 3.465 v v ddq output buffer power supply voltage 3.135 3.3 3.465 v v ih input high voltage 2.0 ? v dd + 0.3 ** v v ih1 input high voltage for mode pin v dd ? 0.3 v dd v dd + 0.3 v v il input low voltage ? 0.3 * ? 0.8 v v il1 input low voltage for mode and nu pins ? 0.3 0.0 0.3 v * : ? 0.7 v with a pulse width of 20% of t kc min (3 ns max) ** : v ddq + 0.7 v with a pulse width of 20% of t kc min (3 ns max) note: the nu pin must be low or not connected. you must not apply a voltage of more than 0.8 v to the nu.
TC55VL836FF-83 2003-02-20 10/21 dc characteristics (ta = = = = 0 to 70c, v dd = = = = v ddq = = = = 3.3 v 5 %) symbol parameter test conditions min typ. max unit i il input leakage current v in = 0 to v dd ? 1 ? 1 a i nu input current (nu pin) v in = 0 to 0.3 v ? 1 ? 1 a i lo output leakage current device deselected or output deselected, v out = 0 to v ddq ? 1 ? 1 a i oh = ? 8 ma 2.4 ? ? v oh output high voltage i oh = ? 100 a v ddq ? 0.2 ? ? v i ol = 8 ma ? ? 0.4 v ol output low voltage i ol = 100 a ? ? 0.2 v i ddo1 operating current i out = 0 ma, all inputs = v dd ? 0.2 v/0.2 v clock t kc minimum ? ? 260 ma i ddo2 operating current (idle) device deselected i out = 0 ma, all inputs = v dd ? 0.2 v/0.2 v clock t kc minimum ? ? 110 ma i dds1 standby current (ttl level) clock = v ss all inputs = v ih or v il ? ? 60 ma i dds2 standby current (mos level) clock = v ss all inputs = v dd ? 0.2 v or 0.2 v ? ? 10 ma i dds3 standby current (snooze mode) zz v dd ? 0.2 v all inputs = v dd ? 0.2 v or 0.2 v clock t kc minimum ? ? 10 ma i dds4 standby current ( cke mode) cke v ih all inputs = v dd ? 0.2 v or 0.2 v clock t kc minimum ? ? 10 ma note: operating current (i ddo1 ) is specified with 50% read cycles and 50% write cycles. capacitance (ta = = = = 25c, f = = = = 1 .0 mhz) symbol parameter test conditions max unit c in input capacitance v in = gnd 5 pf c i/o input/output capacitance v i/o = gnd 7 pf c nu input capacitance of nu v in = gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
TC55VL836FF-83 2003-02-20 11/21 i/o pin c l = 5 pf 217 ? (for enable/disable spec) 3.3 v 295 ? i/o pin c l = 20 pf z 0 = 50 ? 50 ? 1.5 v ac characteristics (ta = = = = 0 to 70c, v dd = = = = v ddq = = = = 3.3 v 5 %) symbol parameter min max unit t kc clk cycle time 12 ? t kh clk high pulse width 4 ? t kl clk low pulse width 4 ? t kqv clk high to output valid ? 9 t kqx clk high to output invalid 3 ? t kqlz clk high to output low-z 4 ? t kqhz clk high to output high-z ? 5 t gqv oe low to output valid ? 5 t gqlz oe low to output low-z 0 ? t gqhz oe high to output high-z ? 5 t as address setup time from clk 2 ? t ds data setup time from clk 1.5 ? t ws we setup time from clk 2 ? t ces ce setup time from clk 2 ? t advs adv setup time from clk 2 ? t bws bw setup time from clk 2 ? t ckes cke setup time from clk 2 ? t ah address hold time from clk 0.5 ? t dh data hold time from clk 0.5 ? t wh we hold time from clk 0.5 ? t ceh ce hold time from clk 0.5 ? t advh adv hold time from clk 0.5 ? t bwh bw hold time from clk 0.5 ? t ckeh cke hold time from clk 0.5 ? t zz zz high to input ignored 0 2t kc t zzr zz low to input sampled 0 2t kc t zzhz zz high to output high-z 0 2t kc t zzlz zz low to output low-z 0 ? ns ac test conditions fig.1 :ac test load fig.2 :ac test load parameter test condition input pulse level 3.0 v/ 0.0 v input pulse rise and fall time 1 v/ns (20%/80%) input timing measurement reference level 1.5 v output timing measurement reference level 1.5 v output load as shown in fig.1 and fig.2
TC55VL836FF-83 2003-02-20 12/21 timing diagrams (1) read cycle cl k address t kh read read read continue deselect read a1 ad v t as bw1 to bw4 cke t gqlz t gqv i/o : don?t care : indeterminate a0 t kl t kc t ah t advs t advh t advs t advh t ws t wh t ckes t ckeh t ces t ceh t ces t ceh t kqx t kqv t kqx t kqhz t kqlz t kqv t kqlz t kqv ce we oe a2 q0 q1 q1 + 1 q1 + 2 read continue read continue q2
TC55VL836FF-83 2003-02-20 13/21 (2) write cycle cl k address t kh write write deselect write a1 ad v t as bw1 to bw4 cke i/o : don?t care : indeterminate a0 t kl t kc t ah t advs t advh t advs t advh t ws t wh t ckes t ckeh t ces t ceh t ces t ceh t ds hi-z ce we oe a2 d0 d1 d1 + 1 d1 + 2 t bws t bwh d2 + 1 t dh write continue write continue write continue d2 t ds t dh
TC55VL836FF-83 2003-02-20 14/21 (3) write/read cycle cl k address t kh write read write write ad v t as bw1 to bw4 cke i/o : don?t care : indeterminate read t kl t kc t ah t advs t advh t ws t wh t ckes t ckeh t ces t ceh ce we oe a0 a1 a2 a3 a4 t bws t bwh d0 q1 d2 q3 q3 + 1 d4 t ds t dh t gqv t gqlz t gqhz t kqlz t kqv t kqhz t kqx write continue read continue d4 + 1 a5
TC55VL836FF-83 2003-02-20 15/21 (4) clock ignore cycle cl k address t kh read write ad v t as bw1 to bw4 cke i/o : don?t care : indeterminate read t kl t kc t ah t ckes t ckeh t ces t ceh ce we t kqlz t kqv a0 a1 a2 t advs t advh t ws t wh t bws t bwh q2 + 3 clock ignore read continue read continue clock ignore read continue t wh t ws t ckes t ckeh q0 d1 q2 + 1 q2 q2 + 2 t kqx t kqhz t ds t dh t kqlz t kqv
TC55VL836FF-83 2003-02-20 16/21 (5) snooze cycle notes: 1. the cycle immediately prior to a snooze brought about by the zz pin must be a read cycle or deselect cycle. 2. memory data is retained during snooze cycles. : don?t care : indeterminate cl k adv t kh zz all inputs (except zz pin) t kl t kc t zzhz t zz deselect or read deselect or read normal t zzr t zzlz dou t
TC55VL836FF-83 2003-02-20 17/21 notes: 1. do not apply opposite data polarity to the i/o pins when they are in the output state. 2. output enable and output disable times are specified as follows using the output load shown in fig.1. (a) t kqlz , t kqhz notes: 1. input states are defined in the synchronous input truth table. 2. when the device is deselected, the output goes into a high impedance state in the present clock cycle regardless of oe . (b) t gqlz , t gqhz , t zzhz ce , ce2 , ce2 dout t gqlz valid data out 0.2 v 0.2 v t gqhz 0.2 v 0.2 v oe , zz t zzhz cl k adv dou t t kqlz t kqhz (see note 1) 0.2 v 0.2 v 0.2 v 0.2 v (see note 1) (see note 2) valid data out
TC55VL836FF-83 2003-02-20 18/21 v ddq = = = = 2.5 v interface specification dc recommended operating conditions (ta = = = = 0 to 70c) symbol parameter min typ. max unit v dd power supply voltage 3.135 3.3 3.465 v v ddq output buffer power supply voltage 2.375 2.5 2.9 v input high voltage for address and control pins 1.7 ? v dd + 0.3 ** v ih input high voltage for i/o pins 1.7 ? v ddq + 0.3 *** v v ih1 input high voltage for mode pin v dd ? 0.3 v dd v dd + 0.3 v v il input low voltage ? 0.3 * ? 0.7 v v il1 input low voltage for mode and nu pins ? 0.3 0.0 0.3 v * : ? 0.7 v with a pulse width of 20% of t kc min (3 ns max) ** : v dd + 0.7 v with a pulse width of 20% of t kc min (3 ns max) *** : v ddq + 0.7 v with a pulse width of 20% of t kc min (3 ns max) note: the nu pin must be low or not connected. you must not apply a voltage of more than 0.8 v to the nu. dc characteristics (ta = = = = 0 to 70c, v dd = = = = 3.3 v 5 %, v ddq = = = = 2.375 v to 2.9 v) symbol parameter test conditions min typ. max unit i il input leakage current v in = 0 to v dd ? 1 ? 1 a i nu input current (nu pin) v in = 0 to 0.3 v ? 1 ? 1 a i lo output leakage current device deselected or output deselected, v out = 0 to v ddq ? 1 ? 1 a i oh = ? 2 ma 1.7 ? ? v oh output high voltage i oh = ? 100 a v ddq ? 0.2 ? ? v i ol = 2 ma ? ? 0.7 v ol output low voltage i ol = 100 a ? ? 0.2 v i ddo1 operating current i out = 0 ma, all inputs = v dd ? 0.2 v/0.2 v clock t kc minimum ? ? 260 ma i ddo2 operating current (idle) device deselected i out = 0 ma, all inputs = v dd ? 0.2 v/0.2 v clock t kc minimum ? ? 110 ma i dds2 standby current (mos level) clock = v ss all inputs = v dd ? 0.2 v or 0.2 v ? ? 10 ma i dds3 standby current (snooze mode) zz v dd ? 0.2 v all inputs = v dd ? 0.2 v or 0.2 v clock t kc minimum ? ? 10 ma i dds4 standby current ( cke mode) cke v ih all inputs = v dd ? 0.2 v or 0.2 v clock t kc minimum ? ? 10 ma note: operating current (i ddo1 ) is specified with 50% read cycles and 50% write cycles.
TC55VL836FF-83 2003-02-20 19/21 i/o pin c l = 5 pf 217 ? (for enable/disable spec) 2.5 v 295 ? i/o pin c l = 20 pf z 0 = 50 ? 50 ? 1.15 v ac characteristics (ta = = = = 0 to 70c, v dd = = = = 3.3 v 5 %, v ddq = = = = 2.375 v to 2.9 v) symbol parameter min max unit t kc clk cycle time 12 ? t kh clk high pulse width 4 ? t kl clk low pulse width 4 ? t kqv clk high to output valid ? 9 t kqx clk high to output invalid 3 ? t kqlz clk high to output low-z 4 ? t kqhz clk high to output high-z ? 5 t gqv oe low to output valid ? 5 t gqlz oe low to output low-z 0 ? t gqhz oe high to output high-z ? 5 t as address setup time from clk 2 ? t ds data setup time from clk 1.5 ? t ws we setup time from clk 2 ? t ces ce setup time from clk 2 ? t advs adv setup time from clk 2 ? t bws bw setup time from clk 2 ? t ckes cke setup time from clk 2 ? t ah address hold time from clk 0.5 ? t dh data hold time from clk 0.5 ? t wh we hold time from clk 0.5 ? t ceh ce hold time from clk 0.5 ? t advh adv hold time from clk 0.5 ? t bwh bw hold time from clk 0.5 ? t ckeh cke hold time from clk 0.5 ? t zz zz high to input ignored 0 2t kc t zzr zz low to input sampled 0 2t kc t zzhz zz high to output high-z 0 2t kc t zzlz zz low to output low-z 0 ? ns ac test conditions fig.1 :ac test load fig.2 :ac test load parameter test condition input pulse level 2.3 v/ 0.0 v input pulse rise and fall time 1 v/ns (20%/80%) input timing measurement reference level 1.15 v output timing measurement reference level 1.15 v output load as shown in fig.1 and fig.2
TC55VL836FF-83 2003-02-20 20/21 package dimensions weight: 0.56 g (typ)
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